As shown in FIG. 12 for example, a probing apparatus serving as one of conventional test devices includes a loader chamber 61 and a prober chamber 62, both of which are arranged adjacent to each other. The loader chamber 61 includes a cassette storage unit for storing wafers W on a cassette-by-cassette basis, a wafer transfer mechanism for loading and unloading the wafers W to and from a cassette one by one, and a pre-alignment mechanism for preliminarily aligning the wafers W while they are transferred by the wafer transfer mechanism. The prober chamber 62 includes a mounting table 63 configured to hold and move a wafer W in X, Y, Z and θ directions, a probe card 64 having a plurality of probes 64A that makes contact with electrode pads of chips formed in the wafer W mounted on the mounting table 63, a fixing mechanism 65 for fixing the probe card 64 by a card holder (not shown), and a connector ring 66 for electrically connecting the probe card 64 to a test head T. Under the control of a control unit, a test on electrical characteristics of the chips is carried out by electrically connecting a tester (not shown) to the chips through the test head T, the connector ring 66 and the probe card 64. In FIG. 12, reference character 67 designates an alignment mechanism that performs position alignment of the wafer W with the probe card 64 in cooperation with the mounting table 63. Reference character 67A designates an upper camera, 67B designates a lower camera and 68 designates a head plate to which the fixing mechanism 65 for fixing the probe card 64 is attached.
In recent years, the wiring structure of a chip becomes minute and highly dense at a rapid pace, and the number of chips formed in a single wafer W has been drastically increased. In view of this, Japanese Patent Laid-open Application Nos. H10-098082 and H05-299485 disclose techniques of enhancing the test efficiency through the use of a probe card capable of testing a plurality of chips at a time.
Disclosed in H10-098082 is a probing method in which a test is performed by bringing a plurality of probes into contact with a plurality of chips on a wafer in an oblique direction. In this probing method, the test is conducted with a probe card confined inside the wafer lest the end portions of the probes should lie outside the marginal portion of the wafer, thereby preventing damage to the probes card which would otherwise occur due to some of the end portions of the probes lying outside the wafer.
Taught in H05-299485 is a probing method capable of shortening a test time by reducing the movement distance of a wafer. In this probing method, probes are prevented from making contact with the same chips more than once. The test starting position in a next row of chips is determined each time a row of chips is changed, which makes it possible to shorten the movement distance of the wafer.
In case of the probing method described in H10-098082, however, some of the probes make contact with a same chip within the wafer more than once. Therefore, there is a need to impose restrictions on the signal transmission and reception not to test the same chip more than once. Another problem resides in that the increased number of contacts between the probes and the chips results in an increase in the movement distance of the wafer. In case of the probing method described in H05-299485, the wafer having chips arranged in rows and columns is repeatedly moved in one row by a distance corresponding to the number of chips tested at a time and is reciprocated by the number of times corresponding to the number of rows of the chips. This poses a problem of increasing the movement distance of the wafer. Another problem posed in the probing method of H05-299485 is that a great deviation occurs in the frequency of use of the probes arranged in the opposite end portions of the probe card.